The present invention relates to a logic integrated circuit technique and, more particularly, to a technique which may effectively be applied to the control of the input and output of data to and from a flip-flop in a LSI logic circuit, for example, a technique which may effectively be utilized for a method of divisionally diagnosing LSI logic circuits such as gate arrays.
A method of diagnosing large-scale integration circuits (LSIs) is known in which the LSI is divided into a plurality of combinational circuits and each of the combinational circuits undergoes a diagnosis.
For example, a master-slave flip-flop which consists of series connected master and slave latches is connected to each of the input and output sides of each of the combinational circuits. Test data is written into the flip-flop at the data input side and input to the combinational circuit, and the output of the combinational circuit is latched by the flip-flop at its output side. This operation is repeated and the latched output is compared with an expected value which has been obtained in advance to thereby diagnose the LSI (see "Nikkei Electronics", Nikkei McGraw-Hill, Apr. 16, 1979, pp. 57 to 63).
The above-described master-slave flip-flop for the divisional diagnosis is arranged such that data which is latched therein is output to the corresponding combinational circuit through a master latch. Further, all the master latches in the logic LSI are controlled by means of in-phase system clock signals so that they can be accessed from external terminals.